About Instruction Scheduling

Code may run slightly faster on the target processor.

Code may run slightly slower on other processors.

You can schedule instructions optimally for specific processor instruction latencies and cache sizes. Using any of these options (shown in the next topic) produces binary code that runs on all processors in the same architecture (IA-32 or Itanium® architecture), but that is optimized for the target processor(s).

When using these options, the compiler optimizes by executing the required operation with the least costly operation, based on the shift/multiply latency of the target processor.