Embedded Target for TI C6000 DSP Release Notes    

Chapter 1
Embedded Target for TI C6000 DSP 2.0 Release Notes

New Features

This section is organized into the following subsections:

Two Virtual Targets Added

Embedded Target for TI C6000 DSP adds support for two virtual target, the C6211 DSP Starter Kit and the C6201 Evaluation module. Both are virtual because you use the C6711 DSK and C6701 EVM with fixed-point blocks to emulate the C6211 DSK and C6211 EVM.

Added C62x DSP Library

The blocks in the C62x DSP Library correspond to functions in the Texas Instruments TMS320C62x DSP Library assembly-code library, which target the TI C62x family of digital signal processors. You can use these blocks to develop simulations by building models in Simulink before generating code. Once a model is developed, you can invoke the Real-Time Workshop to generate code that is optimized to run on the C6711 DSK or C6701 EVM. During code generation, each C62x DSP Library block in your model is mapped to its corresponding TMS320C62x DSP Library assembly-code routine to create target-optimized code. The C62x DSP Library blocks generally input and output fixed-point data types.

The following table list each block in the C62x DSP Library.

Convert Floating-Point to Q.15
Convert a floating-point signal to a Q.15 fixed-point signal
Convert Q.15 to Floating-Point
Convert a Q.15 fixed-point signal to a single-precision floating-point signal
Complex FIR
Filter a complex input signal using a complex FIR filter
General Real FIR
Filter a real input signal using a real FIR filter
LMS Adaptive FIR
Perform least-mean-square adaptive FIR filtering
Radix-4 Real FIR
Filter a real input signal using a real FIR filter
Radix-8 Real FIR
Filter a real input signal using a real FIR filter
Real Forward Lattice All-Pole IIR
Filter a real input signal using an auto-regressive forward lattice filter
Real IIR
Filter a real input signal using a real auto-regressive moving-average IIR filter
Symmetric Real FIR
Filter a real input signal using a symmetric real FIR filter

Math and Matrices

Compute the autocorrelation of an input vector or frame-based matrix
Block Exponent
Return the minimum exponent (number of extra sign bits) found in each channel of an input
Matrix Multiply
Perform matrix multiplication on two input signals
Matrix Transpose
Compute the matrix transpose of an input signal
Compute the fractional and exponential portions of the reciprocal of a real input signal
Vector Dot Product
Compute the vector dot product of two real input signals
Vector Maximum Index
Compute the zero-based index of the maximum value element in each channel of an input signal
Vector Maximum Value
Compute the maximum value for each channel of an input signal
Vector Minimum Value
Compute the minimum value for each channel of an input signal
Vector Multiply
Perform element-wise multiplication on two inputs
Vector Negate
Negate each element of an input signal
Vector Sum of Squares
Compute the sum of squares over each channel of a real input
Weighted Vector Sum
Find the weighted sum of two input vectors
Bit Reverse
Bit-reverse the positions of the elements of each channel of a complex input signal
Compute the decimation-in-frequency forward FFT of a complex input vector
Radix-2 FFT
Compute the radix-2 decimation-in-frequency forward FFT of a complex input vector
Radix-2 IFFT
Compute the radix-2 inverse FFT of a complex input vector

Fixed-Point Code Generation of Product, Sum, and Gain Blocks

The built-in SimulinkTM blocks Gain, Product, and Sum now generate code specifically for fixed-point code generation. This adds more support for generating true fixed-point capable code from the Embedded Target for TI C6000 DSP.

Support for Adding DSP/BIOSTM to Projects

With this release, you can generate code that incorporates DSP/BIOSTM modules and the DSP/BIOS API. Adding the DSP/BIOS functionality lets you take advantage of the modules and tools in DSP/BIOS to provide multithreading, real-time analysis, optimization, and other instrumentation in your Code Composer StudioTM (CCS) projects and executable files. For more information about adding DSP/BIOS to your generated code, refer to "Using DSP/BIOS" in the Embedded Target for TI C6000TM DSP User's Guide.

ADC and DAC Block Requirement Removed

By adding a scheduler to the target software (synchronized to the clock on the board), we have eliminated the requirement that you include at least one ADC or DAC block in the models you develop for targeting. When your model does not include the ADC or DAC blocks, the new scheduler provides the interrupts to trigger events in your model instead of relying on the DMA on the board. Note that the interrupt scheduler assumes that the signal processor clock is running at 100 MHz for the C6701 EVM target or 150 MHz for the C6711 DSK target. If the clock rate does not match the assumed rate, the sample rates in your model will be incorrect and your model will generate incorrect results.

Model Profiling Capability Added

When you build CCS projects that include DSP/BIOS, the Embedded Target for TI C6000 DSP software provides the ability to profile the operation of your generated code.

Invoke the profile capability either from the RTW Options panel in the Simulation Parameters dialog in Simulink, or from the MATLAB command line using profile. For more information on profiling generated code, refer to Profiling Generated Code.

Added Support for Multirate Models Through a Software Scheduler

Now you can create models for targeting that use more than one processing rate. The processing rate of your model can change from the model base rate, such as using decimation or interpolation in your algorithm.

One important note--the target software assumes that your target C6000 digital signal processor (DSP) is running at the factory default rate of 100 MHz when your target is the C6701 EVM and 150 MHz for the C6711 DSK. The scheduler calculates all the interrupt rates for your model using the clock rate. If you change the rate of the DSP clock, the interrupt rates in your model will still be calculated with the base rate, not the one you set. As a result, the rates in your model will be wrong and the results will not be correct. For example, if your model contains a Sine block running at 1 KHz sample rate and your target is your C6701 EVM, the scheduler uses the 100 MHz rate to calculate the interrupt timing to generate the sin wave sampled at 1KHz :

interrupt rate = DSP clock rate/Sine block sample rate

                       = 100 MHz/1KHz

                       = 100 KHz

yielding a sample period of 10 µsec, one interrupt sent to the sine wave generator every 100000 clock cycles.

If your actual clock rate on your C6701 EVM has been reset to 150 MHz, the 10 µsec period is wrong and the sine wave is generated incorrectly.

Inline DSP Blockset Functions Option Added

Code generated from blocks in DSP Blockset use functions in a static run-time library. With this option, you can elect to inline those functions in your generated code. Inlining the functions creates more optimized code at the expense of some increased memory used.

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